1. Field of the Invention
The present invention relates to a semiconductor package technique, in particular, to a chip package structure, a chip package mold chase and a chip package process.
2. Description of Related Art
As for the package of the integrated circuit, the carrier having chips disposed thereon is usually disposed between several mold chases. Then, the mold chases are combined to define a cavity and the carrier and the chips are disposed within the cavity. Thereafter, the molding compound material is injected into the cavity through the pin gates of the mold chases. After the mold chases are removed, the well-known chip package structure is completed. One method for injecting the molding compound material into the cavity is to inject the molding compound material from the tops of the carrier and the chips into the cavity through the pin gate of the top mold chase. The chip package structure comprises the carrier, the chips disposed on the carrier and the molding compound encapsulating a portion of the carrier and the chips.
Generally, after the molding compound material is injected from the tops of the carrier and the chips into the cavity to form the chip package structure and the mold chases are removed, there is a pin gate contact formed at the position on the top surface of the molding compound and the position is corresponding to the pin gate (the pin gate contact is an irregular crack structure formed by removing the excess molding compound from the chip package structure). Additionally, in order to easily identify the leads in the chip package structure in the later process, pin one dot, which is a recess structure, is formed on the top surface of the chip package structure while the chip package structure is formed. According to the current mold chases and the manufacturing process, the pin gate contact is usually located within the range of the pin one dot. Moreover, since the surface of the pin gate contact is rough, it is difficult to identify the pin one dot.